Problem 3 You can choose to answer either option 1 or option 2 in Problem 3. (14 marks) Option 1: 3.a Pipeline Cycle Consider the standard 5 stage pipeline..
3 Problem 3 You can choose to answer either option 1 or option 2 in Problem 3. (14 marks) Option 1: 3.a Pipeline Cycle Consider the standard 5 stage pipeline: Fetch Instruction (IF), Decode Instruction (ID), Execute Instruction (EX), Memory Operation (MEM) and Write back result to regis- ters/memories (WB). Fill in the pipeline table below, which shows the progress of the following instructions through the processor over the clock cycles. You must use * to denote cycles where an instruction is stalled in a pipeline phase. Explain your thoughts of solving this problem. Cycle add $6,$5,$4 and $5,$2,$1 sub $8,$6,$3 sw $4,3($2) lw $5,4($7) or $8,$1,$7 12 13 | 14| 15 16 9. 10 11 3 4 IF | ID | EX IF MEM WB ID EX MEM Hints: This problem is related to the content of cycle pipeline and pipeline hazards. Please refer to the material of lecture 6 in Canvas. You only need to consider Data Hazard in this problem. Please also refer to https://en.wikipedia.org/wiki/Classic_RISC_ pipeline for a description of the basic five-stage pipeline. • The instructions: add, and, sub, sw, lw and or are MIPS instructions and you can refer to http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.htmlto check the detailed information of these instructions. • If cycles number is not enough, you can add more columns to finish these instructions.
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