Design Create a 32-bit ALU in SystemVerilog (follow the approach shown in Figure 5.17). Name the file…
Home/Education/Expert Q&A/Design Create a 32-bit ALU in SystemVerilog (follow the approach shown in Figure 5.17). Name the file…
Create a 32-bit ALU in SystemVerilog (follow the approach shown in Figure 5.17). Name the file alu. sv. It should have the following module declaration:
(input logic [31 0] a, b,
input logic [1 0] ALUControl.
output logic [31:0 ]Result,
output logic [3:0] ALUFlags);
The four bits of ALUFlags should be TRUE if the condition is met. The four flags are as follows:
|3||Result is negative|
|2||Result is 0|
|1||The adder produces a carry out|
|0||The adder results in overflow|
Simulation and Testing
First choose an appropriate set of test vectors to convince a reasonable person that your design is probably correct. I have done this for you in the table given on the following page (you will need to complete the missing values).
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Technifi Expert’s Answer:
module alu (a,b,c) input [31:0] a,b; output [31:0]c; assign c=a+b; end module module top(); reg [31:0]a; reg [31:0]b; write reg[31:0]c;
alu DUT (a,b,c) initial repeat (100)begin a=$random; b=$random; #10 $display (“a=%od,b=%od,c=%od,”a,b,c); if(a+b!=c) $display(“ERROR”); end end module
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